Processor Comparison 1. Investigate the instruction set and architectural features of a modern RISC processor such as the Digital Equipment Corporation Alpha or Motorola/IBM PowerPC. In what ways does it differ from the architecture of the Intel Pentium processor family? The main difference between the architectures of Digital Equipment Corporation’s (DEC) Alpha and Intel’s Pentium processors are the instruction sets. In this paper I intend on defining both RISC and CISC processors. In doing this I will be comparing DEC’s Alpha 21164 (a microprocessor that implements the Alpha architecture) and also Intel’s Pentium processors (from the Pentium-R through the Pentium II). Reduced Instruction Set Computing or RISC processing is a CPU architecture with an instruction set that eliminates some (but not all) complex instructions by pairing down and reducing them in complexity so that instructions can be performed in a single processor cycle.
This is accomplished through high-level compilers that breakdown the more complex, less frequently used instructions into simpler instructions. Thus, allowing the RISC architecture to im-plement a smaller instruction set that utilizes more registers and eliminating the need for microcode. The Alpha architecture is a 64-bit load and store RISC architecture designed with particular emphasis on speed, multiple instruction issue, multiple processors, and software migration from many operating systems. (1, pg. 1-1) Most recent CPU designs are superscalar and superpipelined. Superscalar means that the architecture provides two pipelines for executing multiple instructions in parallel. Superpipelining increases the number of pipeline stages, allowing for results from either pipeline to be simultaneously used to avoid stalls thus, improving data flow by removing data dependency.
The 21164 microprocessor is a superscalar pipelined processor manufactured using 0.5-micron CMOS (Complementary Metal Oxide Semi-conductor) technology. (1, pg.1-3) The Alpha 21164 can issue four instructions in a single clock cycle. This combined with the low-latency and/or high-throughput features in the instruction issue unit and the on-chip components of the memory subsystem reduce the average cycles per instruction. All data manipulation is done between registers. The registers are 64 bits in length and all instructions are 32 bits in length.
Memory operations are either load or store operations. Since many early computers had extremely limited memory and processing power, complex instruction sets were developed. Complex instruction computing or CISC processing is a CPU architecture in which a large number of instructions are hardcoded into the chip. Intel’s Pentium processors still adhere to this philosophy. The Pentium processor was Intel’s first CPU to employ superscalar architecture. With its 3.3 million transistors it is able to execute two instructions per clock cycle resulting in twice the integer performance relative of an Intel 486 CPU running at the same frequency.
Pentium also employed on-chip dual-processing support as well as an onboard interrupt controller. Next came the Pentium Pro, which introduced dynamic execution technology that pre-dicts the program flow through multiple branches. Multiple branch prediction lets the CPU pre-fetch possible next instructions rather than waiting for the outcome. This technology can actually change the order of executed instructions based on analyzed data dependencies, which in turn provides optimum execution speed. However, the Pentium Pro was only available in speeds from 150MHz to 200MHz and has only 16KB of internal cache (half as much as the MMX).
In 1997 Intel introduced the Pentium MMX processor. The MMX processor added1.2 million more transistors (4.5 million total) and also SIMD technology (Single Instruction, Multiple Data). SIMD technology included 57 new instructions, 4 new data types and eight 64-bit registers. As in the original Pentium, the MMX Pentium provides both a fixed-point integer data path that allows up to two operations to be executed simultaneously, and a floating point data path that allows one operation to be performed at a time. In addition, the MMX Pentium provides a new MMX data path that allows up to two MMX operations to execute simultaneously, or up to one MMX operation and one integer operation (in the integer data path) to execute simultaneously.
The inte-ger data path includes two ALUs and supports operations on 8-, 16-, and 32-bit integers. (4) The MMX processor is available in speeds from 166MHz to 333MHz. Finally the Pentium II processor combines the best features of both the Pentium Pro and Pentium MMX on one chip. Including a 64-bit dual independent bus (system bus & cache bus) enhances performance. This was first realized on the Pentium Pro, the pipelined system bus en-ables multiple simultaneous transactions, which accelerates the flow of information within the system and boosts overall performance. Another feature stemming from the Pentium Pro is Dynamic Execution Technology (changing the order of executed instructions based on data dependencies).
With its 7.5 million transistors the Pentium II processors can handle up to 64GB of RAM. “The independent cache bus runs at half the CPU clock, giving a bus speed of 166MHz with a 333MHz processor.” (2) In short, modern RISC processors such as the DEC Alpha 21164 execute many simple instructions by using more registers. RISC processors are able to execute the instructions rela-tively fast due to the use of fixed length instructions. The Alpha for example requires that all instructions are 32 bits in length. Each instruction is loaded and executed before the next.
CISC processors on the other hand, deal with variable length instructions and typically become bloated or bogged down by complicating the job of the control unit. Intel seems to have gotten around this inconvenience by implementing Dynamic Execution Technology and dual independent buses. 1. Choose a commonly used microprocessor such as the Intel Pentium, the DEC Alpha, or the IBM/Motorola PowerPC. What data types are supported? How many bits are used to store each data type? How is each data type internally represented? Through researching Digital Equipment Corporation’s (DEC) Alpha processor I found that the following data types are supported within its architecture: integer, and floating point formats for both IEEE and VAX. I intend to briefly explain what each data type is, how many bits are used to store, and how each data type is internally represented specifically within the DEC Alpha 21164.
The basic addressable unit in the Alpha architecture is the 8-bit byte. Virtual addresses are 64 bits long, howe …